1. Field of the Invention
The present invention relates to a computer program, apparatus, and method for redesigning a logic circuit.
2. Description of the Related Art
Conventionally, FPGAs (Field Programmable Gate Arrays) are used in the development of an LSI (Large Scale Integrated Circuit) such as an ASIC (Application Specific Integrated Circuit). By using FPGAs, it is possible for the developer to redesign a function any number of times to redefine a logic circuit.
When creating a prototype for a large-scale logic circuit, the logic circuit is divided into a plurality of FPGAs or the like. Thus, it is possible to conveniently realize a logic circuit equivalent to the original logic circuit. At this time, it is desirable to divide the logic circuit into FPGAs for each of one or a plurality of specific functions. Doing so is effective, because it is thus possible to perform work such as verification and debugging of the operation of each of the one or a plurality of specific functions.
However, with the above method, although there is no problem in terms of capacity, often the number of pins is insufficient. So, elimination of pin necks is sought.
The methods described in Japanese unexamined patent publication Nos. 11-73440 and 8-30653 are both methods for eliminating pin necks. However, with these methods, it is not possible to eliminate pin necks when the logic circuit is divided into a plurality of FPGAs or the like.